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1 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect ? 1999 fairchild semiconductor corporation nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect designed with permanent write-protection for first 128 bytes for serial presence detect application on memory modules (pc100 compliant) general description the nm34w02 is 2048 bits of cmos non-volatile electrically erasable memory. this device is specifically designed to support serial presence detect circuitry in memory modules. this com- munications protocol uses clock (scl) and data i/o (sda) lines to synchronously clock data between the master (for ex- ample a microprocessor) and the slave eeprom device(s). the contents of the non-volatile memory allows the cpu to determine the capacity of the module and the electrical character- istics of the memory devices it contains. this will enable "plug and play" capability as the module is read and pc main memory resources utilized through the memory controller. the first 128 bytes of the memory of the nm34w02 can be permanently write protected by writing to the "write protect" register. write protect implementation details are described under the section titled addressing the wp register . in addition, like the nm24wxx product family, the entire memory array can be write-protected through "wp" pin. the nm34w02 is available in a jedec standard tssop package for low profile memory modules for systems requiring efficient space utilization such as in a notebook computer. two options are available: l - low voltage and lz - low power, allowing the part to be used in systems where battery life is of primary importance. block diagram features n pc100 compliant n extended operating voltage: 2.7v-5.5v n software write-protection for first 128 bytes n hardware write-protection for entire memory array n 200 m a active current typical C 1.0 m a standby current typical (l) C 0.1 m a standby current typical (lz) n iic compatible interface C provides bidirectional data transfer protocol n sixteen byte page write mode C minimizes total write time per byte n self timed write cycle - typical write cycle time of 6ms n endurance: 1,000,000 data changes n data retention greater than 40 years n packages available: 8-pin tssop and 8-pin so n temperature ranges: commercial and extended ds500078-1 h.v. generation timing &control e 2 prom array 16 x 16 x 8 16 ydec 8 data register xdec control logic word address counter slave address register & comparator start stop logic start cycle 16 4 4 ck d in r/w load inc sda v ss v cc wp d out a2 a1 a0 device address bits 0/1/2/3 scl write protect register march 1999
2 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nm34w02 ds500078-2 so (m8) and tssop (mt8) package connection diagram top view see package number m08a and mtc08 pin names a0,a1,a2 device address inputs v ss ground sda data i/o scl clock input wp write protect v cc power supply ordering information nm 34 w 02 lz e xx letter description package m8 8-pin so8 mt8 8-pin tssop temp. range none 0 to 70 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 4.5v lz 2.7v to 4.5v and <1 m a standby current density 02 2k w full array write protect interface 34 iic nm fairchild non-volatile memory
3 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect product specifications absolute maximum ratings ambient storage temperature C65 c to +150 c all input or output voltages with respect to ground 6.5v to C0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm34w02 0 c to +70 c nm34w02e -40 c to +85 c positive power supply nm34w02 4.5v to 5.5v nm34w02l 2.7v to 4.5v nm34w02lz 2.7v to 4.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current v in = gnd or v cc 10 50 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 100 khz 0.2 1.0 ma i sb standby current for l v in = gnd or v cc 110 m a standby current for lz v in = gnd or v cc 0.1 1 m a i li input leakage current v in = gnd to v cc 0.1 1 m a i lo output leakage current v out = gnd to v cc 0.1 1 m a v il input low voltage C0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
4 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before 4.7 1.3 m s a new transmission can start t hd:sta start condition hold time 4.0 0.6 m s t low clock low period 4.7 1.5 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 m s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 m s t dh data out hold time 300 50 ns t wr write cycle time - nm34w02 10 10 ms (note 3) - nm34w02l, nm34w02lz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm34w02 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device d oes not respond to its slave address.
5 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect bus timing background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. in addition, since the iic bus is designed to support other devices such as ram, eproms, etc., a device type identifier string must follow the start condition. for eeproms, this 4-bit string is 1010. also refer the addressing the wp register section. as shown below, although the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits) on the standard iic. eeprom memory address programming is controlled by 2 methods: ? hardware configuring the a0, a1, and a2 pins (device address pins) with pull-up or pull-down to v cc or v ss . all unused pins must be grounded (tied to v ss ). ? software addressing the required page block within the device memory array (as sent in the slave address string). addressing an eeprom memory location involves sending a command string with the following information: [device type][device address][page block address][byte address] definitions byte 8 bits of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2,048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2,048 bits master any iic device controlling the transfer of data (such as a micropro- cessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) example of 16k of memory on 2-wire bus note: the sda pull-up resistor is required due to the open-drain/open collector output of iic bus devices. the scl pull-up resistor is recommended because of the normal scl line inactive 'high' state. it is recommended that the total line capacitance be less than 400pf. specific timing and addressing considerations are described in greater detail in the following sections. scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto ds500078-5 ds500078-6 sda scl nm34c02l v cc v cc a0 a1 a2 v ss nm24c02 a0 a1 a2 v ss nm24c04 a0 a1 a2 v ss nm24c08 a0 a1 a2 v ss v cc to v cc or v ss to v cc or v ss to v cc or v ss to v cc or v ss v cc v cc v cc
6 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device address pins memory size number of a0 a1 a2 page blocks nm34w02 adr adr adr 2048 bits 1 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wireCored with any number of open drain or open collector outputs. device operation inputs (a0, a1, a2) device address pins a0, a1, and a2 are connected to v cc or v ss to configure the eeprom chip address. table a shows the active pins across the nm34w02 device family. table 1. device a0 a1 a2 effects of addresses nm34w02 adr adr adr 8 devices max. device operation the nm34w02 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm34w02 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm34w02 continuously monitors the sda and scl lines for the start condi- tion and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm34w02 to place the device in the standby power mode. acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 3. the nm34w02 device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm34w02 will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm34w02 slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
7 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 4) . this is fixed as 1010 for all eeprom devices. write cycle timing sda scl stop condition start condition word n 8th bit ack t wr ds500078-7 sda scl start condition stop condition sda scl data stable data change scl from master data output from transmitter data output from receiver 189 start acknowledge ds500078-8 ds500078-9 data validity (figure 1). start and stop definition (figure 2). all iic eeproms use an internal protocol that defines a page block size of 2k bits (for byte addresses 00 through ff). acknowledge responses from receiver (figure 3). ds500078-10
8 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect device addressing (continued) slave addresses (figure 4). refer to the following table for slave address string details: device a0 a1 a2 page page block blocks addresses nm34w02 a a a 1 (2k) (none) write operations the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm34w02 recognizes the start condi- tion, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions. byte write for a write operation a second address field is required which is a byte address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page block of memory. upon receipt of the byte address the nm34w02 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm34w02 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm34w02 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the nm34w02 is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm34w02 will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will 'roll over' and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the hosts write operation the nm34w02 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm34w02 is still busy with the write operation no ack will be returned. if the nm34w02 has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. software write protect software write protection on the nm34w02 protects the first 128 bytes of the eeprom memory. software write protection is implemented through a seperate register called the write pro- tect (wp) register and writing to this wp register permanently write protects the memory. this wp register is a "one-time- only-write" register. once this register is written, it cannot be erased. after the first write to this register, all future access' to this register are ignored as if an invalid iic cycle occured. to write protect, the user must perform a byte write to the wp register. this will permanently disable programming to the first 128 bytes of memory. addressing the wp register addressing the wp register is very similar to accessing any memory array with the following difference: instead of the conventional "1010" iic device address, the unused iic device address "0110" is used to access just the wp register. device address "1010" will be used for all the typical memory array access. with this difference in place, accessing the wp register is same as a typical iic byte write cycle as described under "write operations" section. all timing information and waveform details remain the same. the "byte address" and the "data" fields of the byte write cycle serve as place holders and can be of any value (don't care). refer to figure 7 . hardware write protect programming of the memory will not take place if the wp pin of the nm34w02 is connected to v cc , regardless of whether the soft- ware write protect register has been implemented or not. the nm34w02 will accept slave and word addresses; but if the memory accessed is write protected by the wp pin, the nm34w02 will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. (note: if the wp pin is set to v cc , it will prevent the software write protect register from being written.) device type identifier device address 1 0 1 0 a2 a1 a0 r/w (lsb) nm34w02 ds500078-11
9 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect s t o p bus activity: master sda line data n + 15 data n + 1 data n byte address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line s t o p bus activity: master sda line bus activity: device address data don't care don't care byte address a c k s t a r t slave address a c k a c k ds500078-15 ds500078-16 ds500078-17 write protect scheme (continued) byte write (figure 5). page write (figure 6). wp register write (figure 7). read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm34w02 contains an address counter that main- tains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm34w02 issues an acknowledge and transmits the data byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm34w02 discontinues trans- mission. refer to figure 8 for the sequence of address, acknowl- edge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address, r/w bit set to zero, and then the word address to be read. after the slave word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowl- edge from the nm34w02 and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm34w02 discontinues trans- mission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm34w02 continues to output data for each acknowl- edge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter 'rolls over' and the nm34w02 continues to output data for each acknowledge re- ceived. refer to figure 10 for the address, acknowledge, and data transfer sequence.
10 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect s t o p a c k slave address a c k a c k s t a r t s t a r t byte address slave address bus activity: master sda line data n s t o p a c k bus activity: master sda line a c k data n + x a c k data n + 2 data n +1 data n a c k slave address s t o p data a c k s t a r t slave address bus activity: master sda line ds500078-18 ds500078-19 ds500078-20 sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc ds500078-21 current address read (figure 8) random read (figure 9) sequential read (figure 10) note: due to open drain configuration of sda, a bus-level resistor is called for (typical value = 4.7 w ) typical system configuration (figure 11)
11 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect 8-pin molded small outline package (m8) order number nm34w02lm8/lzm8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
12 www.fairchildsemi.com nm34w02 rev. c.2 nm34w02 2k-bit standard 2-wire bus interface serial eeprom with full array write protect physical dimensions inches (millimeters) unless otherwise noted 8-pin molded tssop, jedec (mt8) order number nm34w02lmt8/lzmt8 package number mtc08 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran?ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x

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